1. Field of the Invention
The present invention relates to a PLO (Phase Locked Oscillator) device, and more particularly, to a PLO device for carrying out clock recovery based on an input signal.
2. Description of the Related Art
A PLO is a circuit wherein feedback control is performed for oscillation so that the phase difference between an input signal supplied from outside and the output of an oscillator within the loop becomes constant, to obtain an oscillating output in phase with the input signal. PLOs are used in various fields such as optical communication field, mobile communication field and digital audio field, and the importance thereof is growing in recent years.
FIG. 41 shows the configuration of a conventional PLO circuit. The PLO circuit 8 comprises a discriminator (comparator) 81, a D-type flip-flop (FF) 82, an exclusive OR gate (EOR) 83, a loop filter 84, and a VCO (Voltage Controlled Oscillator) section 85.
The connections of the elements will be described first. The output of the discriminator 81 is connected to the D terminal of the FF 82 and one input terminal of the EOR 83. The Q terminal of the FF 82 is connected to the other terminal of the EOR 83, the output of which is input to the loop filter 84. The output of the loop filter 84 is input to the VCO section 85, whose output is connected to the clock input terminal of the FF 82.
The discriminator 81 discriminates between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of input signal D0. The FF 82 shifts input data D1 for a time corresponding to half of one time slot, and outputs shifted data D2. The EOR 83 detects the phase difference between the two, phase-shifted and unshifted signals, and outputs difference data D3. The loop filter 84 removes an alternating-current component from the difference data D3 and outputs a direct-current control voltage D4. The VCO section 85 oscillates at an output frequency (input clock for the FF 82) proportional to the control voltage D4.
FIG. 42 is a time chart illustrating operation of the PLO circuit 8. The figure shows the waveforms of the input data D1, shifted data D2, difference data D3 and control voltage D4, which are based on an exemplary sequence pattern of xe2x80x9c0sxe2x80x9d and xe2x80x9c1sxe2x80x9d.
The pulse width of the difference data D3 varies in accordance with a phase difference xcfx86 between the input data D1 and the shifted data D2. Specifically, the pulse width decreases with decrease in the phase difference xcfx86 and increases with increase in the phase difference xcfx86.
The control voltage D4 is a direct-current voltage (solid line) (rectangular wave indicated by the dashed line shows the difference data D3). If the phase difference xcfx86 decreases and the waveform of the shifted data D2 shifts forward relative to the input data D1, then the pulse width of the difference data D3 narrows, so that the control voltage D4 approaches zero.
If the phase difference xcfx86 increases and the waveform of the shifted data D2 shifts backward relative to the input data D1, the pulse width of the difference data D3 widens, and thus the control voltage D4 increases away from zero.
In the PLO circuit 8, the control voltage D4, which is based on the oscillating output, is fed back to the VCO section 85. Thus, control is performed in a manner such that if the oscillating output is delayed, the oscillation frequency is increased to advance the phase, and that if the oscillating output is advanced, the oscillation frequency is decreased to delay the phase, whereby an oscillation frequency in phase with the input signal can be output.
However, the conventional PLO circuit 8 described above is very often adjusted such that clock recovery is carried out based on the input signal D0 having an average pattern (e.g. PN (Pseudo-Noise) pattern etc.) of transition rate, and thus a problem arises in that clock phase change or out-of-phase error occurs when the circuit is input with a signal having a pattern of larger or smaller transition rate.
The transition denotes a level change of the input signal D0 from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, and the transition rate represents the number of level changes per unit time.
FIG. 43 illustrates the relationship between the control voltage D4 and the phase difference xcfx86. The vertical axis indicates the control voltage D4, and the horizontal axis indicates the phase difference xcfx86. The control voltage D4 (solid line) is derived based on the input signal D0, while a control voltage D4-1 (dotted line) is derived based on an input signal (hereinafter referred to as repeating-pattern signal) having a repeating pattern (pattern with large transition rate) in which xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are alternately repeated.
In either case, the control voltage becomes zero when the phase difference xcfx86 is 0 or nxcfx80 (n=xc2x12, xc2x14, . . . ), and rises linearly within one period (pattern is repeated such that the control voltage rises as the phase difference xcfx86 increases within a period and drops to zero at the end of the period).
The repeating-pattern signal has a high frequency of level changes from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, and thus has a larger transition rate than the input signal D0. Accordingly, when the repeating-pattern signal is input to the PLO circuit 8 of FIG. 41, the difference data generated within the circuit through the phase comparison contains an increased high-frequency component, so that the loop filter 84 outputs the control voltage D4-1 which has a larger value than the control voltage D4 derived based on the input signal D0.
FIG. 44 illustrates how clock phase change and out-of-phase error occur. It is assumed that for the control voltage D4 derived based on the input signal D0, a reference voltage Vref, or a threshold, of the VCO section 85 is set approximately at the middle of the inclined straight line of the control voltage D4, and that the reference point is at a position P1 (where normal locking is achievable).
Also, in the figure, H represents a pull-in range (phase controllable range) of the PLO circuit 8. If the varying point of the control voltage D4 is within the pull-in range H, the PLO circuit 8 is capable of normal locking.
On the other hand, if the repeating-pattern signal is input to the PLO circuit 8 and the control voltage D4 changes to a control voltage D4-1a, the reference point shifts from the position P1 to a position P2. In this case, since the reference point is still within the pull-in range H, the phase can be locked but at a position deviated forward, with the result that a clock phase change occurs.
In the case of a control voltage D4-1b with an even greater voltage value, the reference point shifts to a position P3. In this case, since the reference point is outside the pull-in range H, the phase fails to be locked and an out-of-phase error occurs.
In this manner, in cases where a repeating pattern having a large transition rate is input to the PLO circuit 8 which is designed to be supplied with an average transition rate pattern, the PLO circuit 8 malfunctions. Namely, the control voltage is dependent on the transition rate, and therefore, if the transition rate changes, the conventional circuit fails to perform stable operation.
In the foregoing, malfunction attributable to change in the transition rate is explained on the premise that the control voltage is dependent on the transition rate. In practice, however, the control voltage is dependent not only on the transition rate but on S/N (Signal Noise Ratio). Accordingly, if a PLO circuit designed to operate under high S/N conditions is used in poor S/N conditions, the circuit fails to operate normally and a similar malfunction such as clock phase change or out-of-phase error occurs.
The present invention was created in view of the above circumstances, and an object thereof is to provide a PLO device in which parameters related to transition rate and S/N are removed from control voltage to perform high-accuracy, high-quality clock recovery.
To achieve the object, the present invention provides a PLO device for performing clock recovery. The PLO device is characterized by comprising a first voltage detection section which includes a shifted data generation part for shifting input data with use of recovered clock to generate shifted data, a first phase comparison part for comparing phases of the input data and the shifted data with each other and outputting first difference data, and a first filter for removing an alternating-current component from the first difference data and outputting a first detection voltage, a second voltage detection section which includes a delay part for delaying the input data for a time corresponding to half of one time slot with use of an analog delay element and outputting delayed data, a second phase comparison part for comparing phases of the input data and the delayed data with each other and outputting second difference data, and a second filter for removing an alternating-current component from the second difference data and outputting a second detection voltage, an arithmetic section for dividing the first detection voltage by the second detection voltage to obtain a control voltage, and a clock oscillation section for outputting the recovered clock with an oscillation frequency thereof varied in accordance with the control voltage.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.